1. Field of the Invention
The present invention relates to an electric circuit associated with transmission of a clock signal and a method for designing the electric circuit.
2. Description of Related Art
Conventionally, electronic equipment including a personal computer or the like uses a memory device of a standard such as Double Data Rate 2 (DDR2) SDRAM, for instance. A plurality of such memory devices may be disposed in electronic equipment for a purpose of securing sufficient memory capacity or other purposes. A schematic structure of an example of the electric circuit having such the structure is shown in FIG. 2.
The electric circuit includes a control IC 101 and a plurality of (e.g., four) SDRAMs 102a to 102d, which are connected to each other via wirings 103 and 104. In addition, the control IC 101 is provided with a clock signal output portion 111 for outputting a predetermined clock signal and a data input and output portion 112 for supplying or receiving various data to or from the SDRAMs 102a to 102d. 
Such the electric circuit enables the SDRAMs 102a to 102d to read or write data in synchronization with a clock signal (external clock) that is sent from the clock signal output portion 111 via the wiring 103. Note that the clock signal is delivered from the clock signal output portion 111 and is imparted to the SDRAMs 102a to 102d after branching at a branch node 103b. 
In addition, the data input and output portion 112 is supplied with the clock signal from the clock signal output portion 111 and performs input and output of data from or to the SDRAMs 102a to 102d via the wiring 104 in synchronization with the clock signal.
Noting an operation of writing data in the SDRAMs 102a to 102d, for instance, it is desirable that the writing operation should be performed in the SDRAMs 102a to 102d at timings delayed as little as possible from the timing when the data to be written reaches the SDRAMs 102a to 102d via the wirings 104.
However, even if a clock signal that is common to individual operations is used, there may be the case where a time difference occurs between the time period from reception of the clock signal by the data input and output portion 112 until arrival of the data at the SDRAMs 102a to 102d via the wiring 104 and the time period until reception of the clock signal by the SDRAMs 102a to 102d via the wiring 103, due to a delay time of transmission.
Therefore, when such the electric circuit is designed, a wiring length adjustment portion 103a is disposed at each branch of the individual wirings 103 as shown in FIG. 2. This wiring length adjustment portion 103a is disposed for adjusting the length of the wiring 103 so as to adjust transmission delay time of the clock signal (the longer the wiring, the longer the delay time is). According to the wiring length adjustment portion 103a shown in FIG. 2, a meandering pattern is adopted so that the wiring 103 is adjusted to be longer intentionally and that the transmission delay times of the clock signal to the SDRAMs 102a to 102d are increased.
Thus, it is possible to minimize the time difference by adjusting the wiring lengths as described above, so that the operation of writing data in the SDRAMs 102a to 102d can be performed more appropriately. Note that the documents below disclose conventional techniques in the art of the present invention.    JP-A-2004-110103    JP-A-2000-267756    JP-A-2006-54348    JP-A-2000-122751    JP-A-2000-148282
However, if it is necessary to increase the length of the wiring length adjustment portion 103a in the case where the wiring length adjustment portion 103a is disposed at each branch as described above, it is necessary to increase all the plurality of wiring lengths 103a of the individual branches. Therefore, the entire length of the wiring 103 becomes very long, so that power loss will increase due to an increase in wiring resistance. As a result, quantity of current of the clock signal to be supplied to the SDRAMs 102a to 102d may be insufficient.
If the quantity of current of the clock signal is insufficient, it causes drop of an amplitude level of the clock signal or deterioration of a waveform of the clock signal, so that the clock signal cannot be transmitted accurately. Therefore, a malfunction may occur in writing or the like of the data in the SDRAMs 102a to 102d. 